A 5-V Only 16-kbit Stacked-Capacitor MOS RAM

Mitsumasa Koyanagi; Yoshio Sakai; Masamichi Ishihara; Masanori Tazunoki

doi:10.1109/JSSC.1980.1051452

A 5-V Only 16-kbit Stacked-Capacitor MOS RAM

Mitsumasa Koyanagi, Yoshio Sakai, Masamichi Ishihara, Masanori Tazunoki

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

A. novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is called astacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si3N4-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-jum technology and operated successfully. Memory performance is strikingly improved by using STC cells.

Original language	English
Pages (from-to)	661-666
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	15
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.1980.1051452
Publication status	Published - 1980 Aug
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1980.1051452

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title = "A 5-V Only 16-kbit Stacked-Capacitor MOS RAM",

abstract = "A. novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is called astacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si3N4-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-jum technology and operated successfully. Memory performance is strikingly improved by using STC cells.",

author = "Mitsumasa Koyanagi and Yoshio Sakai and Masamichi Ishihara and Masanori Tazunoki",

year = "1980",

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AU - Ishihara, Masamichi

AU - Tazunoki, Masanori

PY - 1980/8

Y1 - 1980/8

N2 - A. novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is called astacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si3N4-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-jum technology and operated successfully. Memory performance is strikingly improved by using STC cells.

AB - A. novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is called astacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si3N4-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-jum technology and operated successfully. Memory performance is strikingly improved by using STC cells.

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ER -

A 5-V Only 16-kbit Stacked-Capacitor MOS RAM

Abstract

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