A 33-ns 64-Mb DRAM

Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

22 Citations (Scopus)


A 64-Mb CMOS DRAM measuring 176.4 mm2 has been fabricated using a 0.4-μm N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. Novel asymmetrical stacked-trench capacitor (AST) cells, 0.9 X 1.7 μm2 each, are laid out in a newly developed PMOS centered interdigitated twisted bit-line (PCITBL) scheme, which achieves both low noise and high packing density. A high-speed 64-Mb CMOS DRAM with 33-ns access time is realized by introducing three new circuit techniques that suppress wiring delays.

Original languageEnglish
Pages (from-to)1498-1505
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Issue number11
Publication statusPublished - 1991 Nov

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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