A 64-Mb CMOS DRAM measuring 176.4 mm2 has been fabricated using a 0.4-μm N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. Novel asymmetrical stacked-trench capacitor (AST) cells, 0.9 X 1.7 μm2 each, are laid out in a newly developed PMOS centered interdigitated twisted bit-line (PCITBL) scheme, which achieves both low noise and high packing density. A high-speed 64-Mb CMOS DRAM with 33-ns access time is realized by introducing three new circuit techniques that suppress wiring delays.
ASJC Scopus subject areas
- Electrical and Electronic Engineering