A 32 X 32-bit Multiplier Using Multiple-valued Mos Current-Mode Circuits

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada

Research output: Contribution to journalArticle

71 Citations (Scopus)

Abstract

A 32 X 32-bit multiplier using Multiplevalued current-mode circuits has been fabricated in 2-üm CMOS technology. For the multiplier based on the radix-4 signed-digit (SD) number system, 32 X 32-bit two's complement multiplication can be performed with only three-stage SD full adders (SDFA's) using a binary-tree addition scheme. The chip contains about 23 600 transistors and the effective multiplier size is about 3.2 X 5.2 mm2, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is comparable to that of the fastest binary multiplier reported.

Original languageEnglish
Pages (from-to)124-132
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume23
Issue number1
DOIs
Publication statusPublished - 1988 Jan 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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