A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme

Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

Research output: Contribution to journalArticlepeer-review

101 Citations (Scopus)

Abstract

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

Original languageEnglish
Article number5437480
Pages (from-to)869-879
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number4
DOIs
Publication statusPublished - 2010 Apr 1

Keywords

  • 2T1R memory cell
  • Localized bi-directional write driver
  • Low-power RAM
  • Nonvolatile RAM
  • Spin-transfer torque
  • TMR
  • Universal memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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