A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

72 Citations (Scopus)

Abstract

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um 2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Circuits, VLSIC 2012
Pages44-45
Number of pages2
DOIs
Publication statusPublished - 2012 Sep 28
Event2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
Duration: 2012 Jun 132012 Jun 15

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1312/6/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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