A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

Shoun Matsunaga; Sadahiko Miura; Hiroaki Honjou; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu

doi:10.1109/VLSIC.2012.6243781

A 3.14 um ² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

88 Citations (Scopus)

Abstract

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um ² under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

Original language	English
Title of host publication	2012 Symposium on VLSI Circuits, VLSIC 2012
Pages	44-45
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243781
Publication status	Published - 2012 Sept 28
Event	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States Duration: 2012 Jun 13 → 2012 Jun 15

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2012 Symposium on VLSI Circuits, VLSIC 2012
Country/Territory	United States
City	Honolulu, HI
Period	12/6/13 → 12/6/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2012.6243781

Cite this

Matsunaga, S., Miura, S., Honjou, H., Kinoshita, K., Ikeda, S., Endoh, T., Ohno, H., & Hanyu, T. (2012). A 3.14 um ² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. In 2012 Symposium on VLSI Circuits, VLSIC 2012 (pp. 44-45). [6243781] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243781

A 3.14 um ² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. / Matsunaga, Shoun; Miura, Sadahiko ; Honjou, Hiroaki et al.

2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 44-45 6243781 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsunaga, S, Miura, S , Honjou, H, Kinoshita, K, Ikeda, S , Endoh, T , Ohno, H & Hanyu, T 2012, A 3.14 um ² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. in 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243781, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 44-45, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 12/6/13. https://doi.org/10.1109/VLSIC.2012.6243781

@inproceedings{0824bd5578a24397a4ef855a78e8a854,

title = "A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture",

abstract = "A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um 2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.",

author = "Shoun Matsunaga and Sadahiko Miura and Hiroaki Honjou and Keizo Kinoshita and Shoji Ikeda and Tetsuo Endoh and Hideo Ohno and Takahiro Hanyu",

year = "2012",

month = sep,

day = "28",

doi = "10.1109/VLSIC.2012.6243781",

language = "English",

isbn = "9781467308458",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "44--45",

booktitle = "2012 Symposium on VLSI Circuits, VLSIC 2012",

note = "2012 Symposium on VLSI Circuits, VLSIC 2012 ; Conference date: 13-06-2012 Through 15-06-2012",

}

TY - GEN

T1 - A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

AU - Matsunaga, Shoun

AU - Miura, Sadahiko

AU - Honjou, Hiroaki

AU - Kinoshita, Keizo

AU - Ikeda, Shoji

AU - Endoh, Tetsuo

AU - Ohno, Hideo

AU - Hanyu, Takahiro

PY - 2012/9/28

Y1 - 2012/9/28

N2 - A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um 2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

AB - A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um 2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

UR - http://www.scopus.com/inward/record.url?scp=84866613380&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866613380&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2012.6243781

DO - 10.1109/VLSIC.2012.6243781

M3 - Conference contribution

AN - SCOPUS:84866613380

SN - 9781467308458

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 44

EP - 45

BT - 2012 Symposium on VLSI Circuits, VLSIC 2012

T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012

Y2 - 13 June 2012 through 15 June 2012

ER -