A 30ns 64Mb DRAM with built-in self-test and repair function

Hiroki Koike, Akira Tanabe, Toshio Takeshima, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A 64 Mw×1 b/16 Mw×4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4μm CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability.

Original languageEnglish
Title of host publicationDigest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages150-151
Number of pages2
ISBN (Electronic)0780305736
DOIs
Publication statusPublished - 1992 Jan 1
Externally publishedYes
Event39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States
Duration: 1992 Feb 191992 Feb 21

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume1992-February
ISSN (Print)0193-6530

Conference

Conference39th IEEE International Solid-State Circuits Conference, ISSCC 1992
CountryUnited States
CitySan Francisco
Period92/2/1992/2/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Koike, H., Tanabe, A., Takeshima, T., Aimoto, Y., Takada, M., Ishijima, T., Kasai, N., Hada, H., Shibahara, K., Kunio, T., Tanigawa, T., Saeki, T., Sakao, M., Miyamoto, H., Nozue, H., Ohya, S., Murotani, T., Koyama, K., & Okuda, T. (1992). A 30ns 64Mb DRAM with built-in self-test and repair function. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 (pp. 150-151). [200456] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.1992.200456