Abstract
A 64-Mb DRAM with a 30-ns access time and 19.48mm x 9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells.
Original language | English |
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Pages (from-to) | 1525-1533 |
Number of pages | 9 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 27 |
Issue number | 11 |
DOIs | |
Publication status | Published - 1992 Nov |
Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering