A 30-ns 64-Mb DRAM with Built-in Self-Test and Self-Repair Function

Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda

Research output: Contribution to journalArticle

50 Citations (Scopus)

Abstract

A 64-Mb DRAM with a 30-ns access time and 19.48mm x 9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells.

Original languageEnglish
Pages (from-to)1525-1533
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number11
DOIs
Publication statusPublished - 1992 Nov
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Tanabe, A., Takeshima, T., Koike, H., Aimoto, Y., Takada, M., Ishijima, T., Kasai, N., Hada, H., Shibahara, K., Kunio, T., Tanigawa, T., Saeki, T., Sakao, M., Miyamoto, H., Nozue, H., Ohya, S., Murotani, T., Koyama, K., & Okuda, T. (1992). A 30-ns 64-Mb DRAM with Built-in Self-Test and Self-Repair Function. IEEE Journal of Solid-State Circuits, 27(11), 1525-1533. https://doi.org/10.1109/4.165332