A 3-ns Range, 8-ps Resolution, Timing Generator LSI Utilizing Si Bipolar Gate Array

Tai Ichi Otsuji, Naoaki Narumi

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

A 3-ns range, 8-ps resolution, timing generator LSI has been realized by using Si bipolar gate arrays. By adopting a redundant weighted delay-unit matrix based on a process-insensitive polynomial formulation, ±2-ps linearity error has been attained at input clock rates of up to 700 MHz. Thermal noise and interconnection crosstalk have been quantitatively investigated as critical factors causing timing error. By adopting the results to the circuit and layout design, thermal jitter and systematic timing error due to crosstalk have been successfully suppressed to less than 8 and ±5 ps, respectively.

Original languageEnglish
Pages (from-to)806-811
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number5
DOIs
Publication statusPublished - 1991 May
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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