A 3-ns range, 8-ps resolution, timing generator LSI has been realized by using Si bipolar gate arrays. By adopting a redundant weighted delay-unit matrix based on a process-insensitive polynomial formulation, ±2-ps linearity error has been attained at input clock rates of up to 700 MHz. Thermal noise and interconnection crosstalk have been quantitatively investigated as critical factors causing timing error. By adopting the results to the circuit and layout design, thermal jitter and systematic timing error due to crosstalk have been successfully suppressed to less than 8 and ±5 ps, respectively.
ASJC Scopus subject areas
- Electrical and Electronic Engineering