A 250 mV bit-line swing scheme for 1-v operating gigabit scale drams

Tsuneo Inaba, Daisaburo Takashima, Yukihito Oowaki, Tohru Ozaklt, Shigeyoshi Watanabe, Takashi Ohsawa, Kazunorî Ohuchi, Hiroyuki Tango

    Research output: Contribution to journalArticlepeer-review


    This paper proposes a small 1/4 Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

    Original languageEnglish
    Pages (from-to)1699-1705
    Number of pages7
    JournalIEICE Transactions on Electronics
    Issue number12
    Publication statusPublished - 1996 Jan 1


    • Bit-line
    • DRAM
    • Memory cell
    • Power dissipation
    • Reliability
    • Sense amplifier
    • Small swing
    • Threshold voltage
    • Wordline

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'A 250 mV bit-line swing scheme for 1-v operating gigabit scale drams'. Together they form a unique fingerprint.

    Cite this