A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture

Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-μm standard CMOS process with 1.5-V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-μm2 bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).

Original languageEnglish
Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages216-219
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Externally publishedYes
Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
Duration: 2007 Nov 122007 Nov 14

Publication series

Name2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
CountryKorea, Republic of
CityJeju
Period07/11/1207/11/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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