TY - GEN
T1 - A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture
AU - Sakimura, Noboru
AU - Sugibayashi, Tadahiko
AU - Nebashi, Ryusuke
AU - Honjo, Hiroaki
AU - Saito, Shinsaku
AU - Kato, Yuko
AU - Kasai, Naoki
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-μm standard CMOS process with 1.5-V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-μm2 bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).
AB - A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-μm standard CMOS process with 1.5-V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-μm2 bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).
UR - http://www.scopus.com/inward/record.url?scp=51349088306&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51349088306&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2007.4425769
DO - 10.1109/ASSCC.2007.4425769
M3 - Conference contribution
AN - SCOPUS:51349088306
SN - 1424413605
SN - 9781424413607
T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
SP - 216
EP - 219
BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Y2 - 12 November 2007 through 14 November 2007
ER -