A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture

Noboru Sakimura; Tadahiko Sugibayashi; Ryusuke Nebashi; Hiroaki Honjo; Shinsaku Saito; Yuko Kato; Naoki Kasai

doi:10.1109/ASSCC.2007.4425769

A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture

Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-μm standard CMOS process with 1.5-V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-μm² bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	216-219
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425769
Publication status	Published - 2007 Dec 1
Externally published	Yes
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 2007 Nov 12 → 2007 Nov 14

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	07/11/12 → 07/11/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2007.4425769

Cite this

Sakimura, N., Sugibayashi, T., Nebashi, R., Honjo, H., Saito, S., Kato, Y., & Kasai, N. (2007). A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 216-219). [4425769] (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425769

A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture. / Sakimura, Noboru; Sugibayashi, Tadahiko; Nebashi, Ryusuke et al.

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. p. 216-219 4425769 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sakimura, N, Sugibayashi, T, Nebashi, R, Honjo, H, Saito, S, Kato, Y & Kasai, N 2007, A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425769, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 216-219, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 07/11/12. https://doi.org/10.1109/ASSCC.2007.4425769

Sakimura N, Sugibayashi T, Nebashi R, Honjo H, Saito S, Kato Y et al. A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2007. p. 216-219. 4425769. (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425769

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abstract = "A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-μm standard CMOS process with 1.5-V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-μm2 bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).",

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A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture

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