Abstract
A NAND structure memory cell with 2.2 × 1.05 μm2 size per bit, based on a 0.6 μm design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 μm space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.
| Original language | English |
|---|---|
| Pages (from-to) | 103-106 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting |
| Publication status | Published - 1990 Dec 1 |
| Externally published | Yes |
| Event | 1990 International Electron Devices Meeting - San Francisco, CA, USA Duration: 1990 Dec 9 → 1990 Dec 12 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
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Cite this
Shirota, R., Nakayama, R., Kirisawa, R., Momodomi, M., Sakui, K., Itoh, Y., Aritome, S., Endoh, T., Hatori, F., & Masuoka, F. (1990). A 2.3 μm2 memory cell structure for 16 Mb NAND EEPROMs. Technical Digest - International Electron Devices Meeting, 103-106.