A 2.3 μm2 memory cell structure for 16 Mb NAND EEPROMs

R. Shirota; R. Nakayama; R. Kirisawa; M. Momodomi; K. Sakui; Y. Itoh; S. Aritome; T. Endoh; F. Hatori; F. Masuoka

A 2.3 μm² memory cell structure for 16 Mb NAND EEPROMs

R. Shirota, R. Nakayama, R. Kirisawa, M. Momodomi, K. Sakui, Y. Itoh, S. Aritome, T. Endoh, F. Hatori, F. Masuoka

Research output: Contribution to journal › Conference article › peer-review

Abstract

A NAND structure memory cell with 2.2 × 1.05 μm² size per bit, based on a 0.6 μm design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 μm space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.

Original language	English
Pages (from-to)	103-106
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1990 Dec 1
Externally published	Yes
Event	1990 International Electron Devices Meeting - San Francisco, CA, USA Duration: 1990 Dec 9 → 1990 Dec 12

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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title = "A 2.3 μm2 memory cell structure for 16 Mb NAND EEPROMs",

abstract = "A NAND structure memory cell with 2.2 × 1.05 μm2 size per bit, based on a 0.6 μm design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 μm space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.",

author = "R. Shirota and R. Nakayama and R. Kirisawa and M. Momodomi and K. Sakui and Y. Itoh and S. Aritome and T. Endoh and F. Hatori and F. Masuoka",

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language = "English",

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journal = "Technical Digest - International Electron Devices Meeting",

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T1 - A 2.3 μm2 memory cell structure for 16 Mb NAND EEPROMs

AU - Shirota, R.

AU - Nakayama, R.

AU - Kirisawa, R.

AU - Momodomi, M.

AU - Sakui, K.

AU - Itoh, Y.

AU - Aritome, S.

AU - Endoh, T.

AU - Hatori, F.

AU - Masuoka, F.

PY - 1990/12/1

Y1 - 1990/12/1

N2 - A NAND structure memory cell with 2.2 × 1.05 μm2 size per bit, based on a 0.6 μm design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 μm space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.

AB - A NAND structure memory cell with 2.2 × 1.05 μm2 size per bit, based on a 0.6 μm design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 μm space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.

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T2 - 1990 International Electron Devices Meeting

Y2 - 9 December 1990 through 12 December 1990

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A 2.3 μm2 memory cell structure for 16 Mb NAND EEPROMs

Abstract

ASJC Scopus subject areas

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A 2.3 μm² memory cell structure for 16 Mb NAND EEPROMs