A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic

Takahiro Hanyu, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

85 Citations (Scopus)

Abstract

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54 × 54-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-µm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit.

Original languageEnglish
Pages (from-to)1239-1245
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume30
Issue number11
DOIs
Publication statusPublished - 1995 Nov

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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