A 200-μV/e- CMOS image sensor with 100-ke- full well capacity

Satoru Adachi, Woonghee Lee, Nana Akahane, Hiromichi Oshikubo, Koichi Mizobuchi, Shigetoshi Sugawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)


A high sensitivity CMOS image sensor without the dynamic range (DR) trade-off has been developed by implementing the small floating diffusion (FD) capacitance in the lateral overflow integration capacitor (CS) embedded pixel circuit. A 1/4-inch VGA chip fabricated through 0.18-μm 2P3M process achieves 200-μV/e- conversion gain with 100-ke- full well capacity, 2.2-e-mis noise floor and 93-dB DR. The S/N ratio degradation at the detection node switch from FD to FD+CS is not visible.

Original languageEnglish
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2007 Dec 1
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: 2007 Jun 142007 Jun 16

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2007 Symposium on VLSI Circuits, VLSIC


  • CMOS image sensor
  • Dynamic range
  • Sensitivity

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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