A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry

Akira Mochizuki, Takahiro Hanyu

Research output: Contribution to conferencePaper

13 Citations (Scopus)

Abstract

This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

Original languageEnglish
Pages264-267
Number of pages4
DOIs
Publication statusPublished - 2005 Dec 1
Event2005 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2005 Jun 162005 Jun 18

Other

Other2005 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period05/6/1605/6/18

Keywords

  • Conditional sum adder and crosstalk noise reduction
  • Current-mode logic
  • Signed-digit number

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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