A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm CMOS

Naoto Miyamoto, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In this paper, we propose a dynamically reconfigurable multi-context FPGA core named Flexible Processor IV (FP4). FP4 contains 16 x 16 physical logic elements (LE) and 16 context memory planes, thus virtually 4,096 LEs are available in total. The core size is only 1.36mm x 1.15mm in 90 nm CMOS technology. A critical issue of FP4 is to prevent the fall of multi-context execution speed. Therefore we have developed a shift-register-type temporal communication module (SR-TCM) and a design automation software named PELOC. PELOC can divide a circuit larger than the physical capacity of FP4 to several smaller sub-circuits while maintaining critical path delay equal among all the sub-circuits. By using the SRTCM and PELOC, we confirmed that the execution speed of FP4 is almost constant regardless of the number of contexts used.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages89-92
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period08/11/308/11/5

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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