TY - GEN
T1 - A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology
AU - Fujimoto, Ryuichi
AU - Motoyoshi, Mizuki
AU - Yodprasit, Uroschanit
AU - Takano, Kyoya
AU - Fujishima, Minoru
PY - 2010/12/1
Y1 - 2010/12/1
N2 - The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.
AB - The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.
UR - http://www.scopus.com/inward/record.url?scp=79952849570&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2010.5716610
DO - 10.1109/ASSCC.2010.5716610
M3 - Conference contribution
AN - SCOPUS:79952849570
SN - 9781424482979
T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
SP - 281
EP - 284
BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Y2 - 8 November 2010 through 10 November 2010
ER -