A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology

Ryuichi Fujimoto, Mizuki Motoyoshi, Uroschanit Yodprasit, Kyoya Takano, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Abstract

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages281-284
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Externally publishedYes
Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
Duration: 2010 Nov 82010 Nov 10

Publication series

Name2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Other

Other2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
CountryChina
CityBeijing
Period10/11/810/11/10

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Fujimoto, R., Motoyoshi, M., Yodprasit, U., Takano, K., & Fujishima, M. (2010). A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 281-284). [5716610] (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716610