A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology

Ryuichi Fujimoto; Mizuki Motoyoshi; Uroschanit Yodprasit; Kyoya Takano; Minoru Fujishima

doi:10.1109/ASSCC.2010.5716610

A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology

Ryuichi Fujimoto, Mizuki Motoyoshi, Uroschanit Yodprasit, Kyoya Takano, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Citations (Scopus)

Abstract

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10^-9.

Original language	English
Title of host publication	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages	281-284
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716610
Publication status	Published - 2010 Dec 1
Externally published	Yes
Event	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China Duration: 2010 Nov 8 → 2010 Nov 10

Publication series

Name	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Other

Other	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country/Territory	China
City	Beijing
Period	10/11/8 → 10/11/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASSCC.2010.5716610

Cite this

A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology. / Fujimoto, Ryuichi; Motoyoshi, Mizuki; Yodprasit, Uroschanit et al.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 281-284 5716610 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujimoto, R, Motoyoshi, M, Yodprasit, U, Takano, K & Fujishima, M 2010, A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716610, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 281-284, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 10/11/8. https://doi.org/10.1109/ASSCC.2010.5716610

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AU - Fujishima, Minoru

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AB - The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

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A 120-GHz transmitter and receiver chipset with 9-Gps data rate using 65-nm CMOS technology

Abstract

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