A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo

Research output: Contribution to journalConference articlepeer-review

8 Citations (Scopus)

Abstract

This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm × 9.7 mm die using the 0.13-μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

Original languageEnglish
Pages (from-to)177-180
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 2003
Externally publishedYes
EventProceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 2003 Sep 212003 Sep 24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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