A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

Hiroe Iwasaki; Jiro Naganuma; Yasuyuki Nakajima; Yutaka Tashiro; Ken Nakamura; Takeshi Yoshitome; Takayuki Onishi; Mitsuo Ikeda; Takaaki Izuoka; Makoto Endo

A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo

Research output: Contribution to journal › Conference article › peer-review

8 Citations (Scopus)

Abstract

This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm × 9.7 mm die using the 0.13-μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

Original language	English
Pages (from-to)	177-180
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 2003
Externally published	Yes
Event	Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States Duration: 2003 Sep 21 → 2003 Sep 24

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems",

abstract = "This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm × 9.7 mm die using the 0.13-μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.",

author = "Hiroe Iwasaki and Jiro Naganuma and Yasuyuki Nakajima and Yutaka Tashiro and Ken Nakamura and Takeshi Yoshitome and Takayuki Onishi and Mitsuo Ikeda and Takaaki Izuoka and Makoto Endo",

year = "2003",

language = "English",

pages = "177--180",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 2003 Custom Integrated Circuits Conference ; Conference date: 21-09-2003 Through 24-09-2003",

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T1 - A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

AU - Iwasaki, Hiroe

AU - Naganuma, Jiro

AU - Nakajima, Yasuyuki

AU - Tashiro, Yutaka

AU - Nakamura, Ken

AU - Yoshitome, Takeshi

AU - Onishi, Takayuki

AU - Ikeda, Mitsuo

AU - Izuoka, Takaaki

AU - Endo, Makoto

PY - 2003

Y1 - 2003

N2 - This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm × 9.7 mm die using the 0.13-μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

AB - This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm × 9.7 mm die using the 0.13-μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

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M3 - Conference article

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EP - 180

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

SN - 0886-5930

T2 - Proceedings of the IEEE 2003 Custom Integrated Circuits Conference

Y2 - 21 September 2003 through 24 September 2003

ER -

A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

Abstract

ASJC Scopus subject areas

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