A 100dB DR CMOS Image Sensor Using a Lateral Overflow Integration Capacitor

Shigetoshi Sugawa; Nana Akahane; Satoru Adachi; Kazuya Mori; Toshiyuki Ishiuchi; Koichi Mizobuchi

A 100dB DR CMOS Image Sensor Using a Lateral Overflow Integration Capacitor

Shigetoshi Sugawa, Nana Akahane, Satoru Adachi, Kazuya Mori, Toshiyuki Ishiuchi, Koichi Mizobuchi

ENG - Management Science and Technology

Research output: Contribution to journal › Conference article › peer-review

10 Citations (Scopus)

Abstract

The wide DR CMOS image sensor incorporates a lateral overflow capacitor in each pixel to integrate the overflow charges from the photodiode when it saturates. The 7.5×7.5μm² pixel, 1/3" VGA sensor fabricated in a 0.35μm 3M2P CMOS process achieves a 100dB dynamic range with no image lag, 0.15mV_rms random noise and 0.15mV fixed pattern noise.

Original language	English
Article number	19.4
Pages (from-to)	288-289
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
Publication status	Published - 2005 Dec 6
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2005 Feb 6 → 2005 Feb 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

A 100dB DR CMOS Image Sensor Using a Lateral Overflow Integration Capacitor. / Sugawa, Shigetoshi; Akahane, Nana; Adachi, Satoru; Mori, Kazuya; Ishiuchi, Toshiyuki; Mizobuchi, Koichi.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 48, 19.4, 06.12.2005, p. 288-289.

Research output: Contribution to journal › Conference article › peer-review

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AU - Ishiuchi, Toshiyuki

AU - Mizobuchi, Koichi

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AB - The wide DR CMOS image sensor incorporates a lateral overflow capacitor in each pixel to integrate the overflow charges from the photodiode when it saturates. The 7.5×7.5μm2 pixel, 1/3" VGA sensor fabricated in a 0.35μm 3M2P CMOS process achieves a 100dB dynamic range with no image lag, 0.15mVrms random noise and 0.15mV fixed pattern noise.

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T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

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A 100dB DR CMOS Image Sensor Using a Lateral Overflow Integration Capacitor

Abstract

ASJC Scopus subject areas

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