A 100 MHz 7.84 mm2 31.7 msec 439 mW 512-point 2-dimensional FFT single-chip processor

Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multi-datapath radix-23 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8×2.8 mm2 with CMOS 0.35 μm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensonal FFT in 23.2 μsec and a 2-dimensional one in only 23.8 msec at 133 MHz operation. The power consumption of this processor is 439.6 mW at 3.3 V, 100 MHz operation.

Original languageEnglish
Pages (from-to)502-509
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE87-C
Issue number4
Publication statusPublished - 2004 Apr

Keywords

  • Cached-memory architecture
  • Double buffer structure
  • Fast Fourier transform

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 100 MHz 7.84 mm<sup>2</sup> 31.7 msec 439 mW 512-point 2-dimensional FFT single-chip processor'. Together they form a unique fingerprint.

Cite this