A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch

Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Kazuyasu Nishikawa, Eiji Taniguchi, Hiroomi Ueda, Masayoshi Ono, Jun Tomisawa, Yoshikazu Yoneda, Yasushi Hashizume, Kazuyuki Sugahara, Noriharu Suematsu, Tatsuo Oomori

Research output: Contribution to conferencePaperpeer-review

6 Citations (Scopus)

Abstract

The highest performance to date of any switch using a CMOS process, of a 0.8dB insertion-loss, 23dB isolation and 17.4dBm power-handling capability at 5GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using Depletion-layer-Extended Transistors (DETs) in a 0.18μm CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

Original languageEnglish
Pages229-232
Number of pages4
Publication statusPublished - 2003 Aug 25
Externally publishedYes
Event2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Philadelphia, PA, United States
Duration: 2003 Jun 82003 Jun 10

Other

Other2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
CountryUnited States
CityPhiladelphia, PA
Period03/6/803/6/10

ASJC Scopus subject areas

  • Engineering(all)

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