A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch

Takahiro Ohnakado; Satoshi Yamakawa; Takaaki Murakami; Akihiko Furukawa; Kazuyasu Nishikawa; Eiji Taniguchi; Hiroomi Ueda; Masayoshi Ono; Jun Tomisawa; Yoshikazu Yoneda; Yasushi Hashizume; Kazuyuki Sugahara; Noriharu Suematsu; Tatsuo Oomori

A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch

Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Kazuyasu Nishikawa, Eiji Taniguchi, Hiroomi Ueda, Masayoshi Ono, Jun Tomisawa, Yoshikazu Yoneda, Yasushi Hashizume, Kazuyuki Sugahara, Noriharu Suematsu, Tatsuo Oomori

Research output: Contribution to conference › Paper › peer-review

6 Citations (Scopus)

Abstract

The highest performance to date of any switch using a CMOS process, of a 0.8dB insertion-loss, 23dB isolation and 17.4dBm power-handling capability at 5GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using Depletion-layer-Extended Transistors (DETs) in a 0.18μm CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

Original language	English
Pages	229-232
Number of pages	4
Publication status	Published - 2003 Aug 25
Externally published	Yes
Event	2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Philadelphia, PA, United States Duration: 2003 Jun 8 → 2003 Jun 10

Other

Other	2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
Country	United States
City	Philadelphia, PA
Period	03/6/8 → 03/6/10

ASJC Scopus subject areas

Engineering(all)

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Ohnakado, T., Yamakawa, S., Murakami, T., Furukawa, A., Nishikawa, K., Taniguchi, E., Ueda, H., Ono, M., Tomisawa, J., Yoneda, Y., Hashizume, Y., Sugahara, K., Suematsu, N., & Oomori, T. (2003). A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch. 229-232. Paper presented at 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, United States.

A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch. / Ohnakado, Takahiro; Yamakawa, Satoshi; Murakami, Takaaki; Furukawa, Akihiko; Nishikawa, Kazuyasu; Taniguchi, Eiji; Ueda, Hiroomi; Ono, Masayoshi; Tomisawa, Jun; Yoneda, Yoshikazu; Hashizume, Yasushi; Sugahara, Kazuyuki; Suematsu, Noriharu; Oomori, Tatsuo.

2003. 229-232 Paper presented at 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, United States.

Research output: Contribution to conference › Paper › peer-review

Ohnakado, T, Yamakawa, S, Murakami, T, Furukawa, A, Nishikawa, K, Taniguchi, E, Ueda, H, Ono, M, Tomisawa, J, Yoneda, Y, Hashizume, Y, Sugahara, K, Suematsu, N & Oomori, T 2003, 'A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch', Paper presented at 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, United States, 03/6/8 - 03/6/10 pp. 229-232.

Ohnakado, Takahiro ; Yamakawa, Satoshi ; Murakami, Takaaki ; Furukawa, Akihiko ; Nishikawa, Kazuyasu ; Taniguchi, Eiji ; Ueda, Hiroomi ; Ono, Masayoshi ; Tomisawa, Jun ; Yoneda, Yoshikazu ; Hashizume, Yasushi ; Sugahara, Kazuyuki ; Suematsu, Noriharu ; Oomori, Tatsuo. / A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch. Paper presented at 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, United States.4 p.

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abstract = "The highest performance to date of any switch using a CMOS process, of a 0.8dB insertion-loss, 23dB isolation and 17.4dBm power-handling capability at 5GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using Depletion-layer-Extended Transistors (DETs) in a 0.18μm CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.",

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AU - Furukawa, Akihiko

AU - Nishikawa, Kazuyasu

AU - Taniguchi, Eiji

AU - Ueda, Hiroomi

AU - Ono, Masayoshi

AU - Tomisawa, Jun

AU - Yoneda, Yoshikazu

AU - Hashizume, Yasushi

AU - Sugahara, Kazuyuki

AU - Suematsu, Noriharu

AU - Oomori, Tatsuo

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AB - The highest performance to date of any switch using a CMOS process, of a 0.8dB insertion-loss, 23dB isolation and 17.4dBm power-handling capability at 5GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using Depletion-layer-Extended Transistors (DETs) in a 0.18μm CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

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A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch

Abstract

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