A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Kazuyasu Nishikawa, Eiji Taniguchi, Hiroomi Ueda, Masayoshi Ono, Jun Tomisawa, Yoshikazu Yoneda, Yasushi Hashizume, Kazuyuki Sugahara, Noriharu Suematsu, Tatsuo Oomori

Research output: Contribution to journalLetterpeer-review

5 Citations (Scopus)

Abstract

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 μm CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

Original languageEnglish
Pages (from-to)192-194
Number of pages3
JournalIEEE Electron Device Letters
Volume24
Issue number3
DOIs
Publication statusPublished - 2003 Mar 1
Externally publishedYes

Keywords

  • CMOS integrated circuits
  • MOSFETS
  • Microwave circuits
  • Microwave devices
  • Switches

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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