A 0.602 um2 nestled Chain cell structure formed by one mask etching process for 64 Mbit FeRAM

H. Kanaya, K. Tomioka, T. Matsushita, M. Omura, T. Ozaki, Y. Kumura, Y. Shimojo, T. Morimoto, O. Hidaka, S. Shuto, H. Koyama, Y. Yamada, K. Osari, N. Tokoh, F. Fujisaki, N. Iwabuchi, N. Yamaguchi, T. Watanabe, M. Yabuki, H. ShinomiyaN. Watanabe, E. Itoh, T. Tsuchiya, K. Yamakawa, K. Natori, S. Yamazaki, K. Nakazawa, D. Takashima, S. Shiratake, S. Ohtsuki, Y. Oowaki, I. Kunishima, A. Nitayama

Research output: Contribution to journalConference articlepeer-review

17 Citations (Scopus)

Abstract

We have successfully developed a 0.602 um2 nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the 'Chain' FeRAM, a pair of capacitors on a same node can be nestled close to each other. A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602um2. The cell size was reduced to 32% of previous work. Signal window of 600mV was obtained by the nestled 'Chain' FeRAM structure after full integration of three-metal CMOS technology.

Original languageEnglish
Pages (from-to)150-151
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2004
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: 2004 Jun 152004 Jun 17

Keywords

  • Chain
  • FeRAM
  • Ir
  • IrO
  • One mask etching
  • W-plug

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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