A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)

L. Nesbit, J. Alsmeier, B. Chen, J. DeBrosse, P. Fahey, M. Gall, J. Gambino, S. Gernhardt, H. Ishiuchi, R. Kleinhenz, J. Mandelman, T. Mii, M. Morikado, A. Nitayama, S. Parke, H. Wong, G. Bronner

Research output: Contribution to journalConference articlepeer-review

39 Citations (Scopus)

Abstract

In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd STrap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 µm2 at 0.25 µm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 µm design rules, are presented in this paper.

Original languageEnglish
Pages (from-to)627-630
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
Publication statusPublished - 1993
Externally publishedYes
EventProceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA
Duration: 1993 Dec 51993 Dec 8

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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