A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh

    Research output: Contribution to conferencePaperpeer-review

    3 Citations (Scopus)

    Abstract

    We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size - fabricated by using 0.13-μm technology - is 0. 78 μm2, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.

    Original languageEnglish
    Pages60-63
    Number of pages4
    Publication statusPublished - 2004 Sep 29
    Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
    Duration: 2004 Jun 172004 Jun 19

    Other

    Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
    CountryUnited States
    CityHonolulu, HI
    Period04/6/1704/6/19

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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