80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue, M. Inuishi

Research output: Contribution to journalConference articlepeer-review

11 Citations (Scopus)

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