7.7-ps CML using selective-epitaxial SiGe HBTs

Eiji Ohue, Katsuya Oda, Reiko Hayami, Katsuyoshi Washio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

The fastest CML-gate delay to date (7.7 ps) was achieved. This CML gate uses a fully-self-aligned SiGe-base HBT (with a 92-GHz cutoff frequency and a 108-GHz maximum oscillation frequency) with a selectively-implanted collector through the base.

Original languageEnglish
Title of host publicationProceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting
Editors Anon
PublisherIEEE
Pages97-100
Number of pages4
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
Duration: 1998 Sep 271998 Sep 29

Other

OtherProceedings of the 1998 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period98/9/2798/9/29

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Ohue, E., Oda, K., Hayami, R., & Washio, K. (1998). 7.7-ps CML using selective-epitaxial SiGe HBTs. In Anon (Ed.), Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (pp. 97-100). IEEE.