7.03-μm2 Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

K. Shoji, M. Moniwa, H. Yamashita, T. Kisu, T. Kaga, K. Torii, T. Kumihashi, T. Morimoto, H. Kawakami, Y. Gotoh, T. Itoga, T. Tanaka, N. Yokoyama, T. Kure, M. Ohkura, al et al

    Research output: Contribution to journalConference article

    15 Citations (Scopus)

    Abstract

    A ferroelectric memory cell with an area of only 7.03 μm2 designed with a 0.5-μm rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation[1]: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr = 50 fC/bit) and achieves ferroelectric write/read under ±2.5-V operation in 4-K bit memory cell arrays.

    Original languageEnglish
    Pages (from-to)28-29
    Number of pages2
    JournalDigest of Technical Papers - Symposium on VLSI Technology
    Publication statusPublished - 1996 Jan 1
    EventProceedings of the 1996 Symposium on VLSI Technology - Honolulu, HI, USA
    Duration: 1996 Jun 111996 Jun 13

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of '7.03-μm<sup>2</sup> Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching'. Together they form a unique fingerprint.

  • Cite this

    Shoji, K., Moniwa, M., Yamashita, H., Kisu, T., Kaga, T., Torii, K., Kumihashi, T., Morimoto, T., Kawakami, H., Gotoh, Y., Itoga, T., Tanaka, T., Yokoyama, N., Kure, T., Ohkura, M., & et al, A. (1996). 7.03-μm2 Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching. Digest of Technical Papers - Symposium on VLSI Technology, 28-29.