A ferroelectric memory cell with an area of only 7.03 μm2 designed with a 0.5-μm rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr = 50 fC/bit) and achieves ferroelectric write/read under ±2.5-V operation in 4-K bit memory cell arrays.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 1996 Jan 1|
|Event||Proceedings of the 1996 Symposium on VLSI Technology - Honolulu, HI, USA|
Duration: 1996 Jun 11 → 1996 Jun 13
ASJC Scopus subject areas
- Electrical and Electronic Engineering