64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics

S. Kobayashi, K. Amanuma, H. Mori, N. Kasai, Y. Maejima, A. Seike, N. Tanabe, T. Tatsumi, J. Yamada, T. Miwa, H. Koike, H. Hada, H. Toyoshima

Research output: Contribution to journalConference articlepeer-review

11 Citations (Scopus)


Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64Kbit CMVP FeRAM macro is integrated with 0.35μm 3-level metallization CMOS logic devices. The ferroeletric properties of the PZT capacitor formed below 430°C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25°C and 150°C with write/read voltages between 2.7V and 5.5V.

Original languageEnglish
Pages (from-to)783-786
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2000 Dec 1
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 2000 Dec 102000 Dec 13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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