64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics

S. Kobayashi; K. Amanuma; H. Mori; N. Kasai; Y. Maejima; A. Seike; N. Tanabe; T. Tatsumi; J. Yamada; T. Miwa; H. Koike; H. Hada; H. Toyoshima

64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics

S. Kobayashi, K. Amanuma, H. Mori, N. Kasai, Y. Maejima, A. Seike, N. Tanabe, T. Tatsumi, J. Yamada, T. Miwa, H. Koike, H. Hada, H. Toyoshima

Research output: Contribution to journal › Conference article › peer-review

11 Citations (Scopus)

Abstract

Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64Kbit CMVP FeRAM macro is integrated with 0.35μm 3-level metallization CMOS logic devices. The ferroeletric properties of the PZT capacitor formed below 430°C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25°C and 150°C with write/read voltages between 2.7V and 5.5V.

Original language	English
Pages (from-to)	783-786
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2000 Dec 1
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 2000 Dec 10 → 2000 Dec 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics. / Kobayashi, S.; Amanuma, K.; Mori, H.; Kasai, N.; Maejima, Y.; Seike, A.; Tanabe, N.; Tatsumi, T.; Yamada, J.; Miwa, T.; Koike, H.; Hada, H.; Toyoshima, H.

In: Technical Digest - International Electron Devices Meeting, 01.12.2000, p. 783-786.

Research output: Contribution to journal › Conference article › peer-review

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title = "64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics",

abstract = "Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64Kbit CMVP FeRAM macro is integrated with 0.35μm 3-level metallization CMOS logic devices. The ferroeletric properties of the PZT capacitor formed below 430°C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25°C and 150°C with write/read voltages between 2.7V and 5.5V.",

author = "S. Kobayashi and K. Amanuma and H. Mori and N. Kasai and Y. Maejima and A. Seike and N. Tanabe and T. Tatsumi and J. Yamada and T. Miwa and H. Koike and H. Hada and H. Toyoshima",

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journal = "Technical Digest - International Electron Devices Meeting",

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T1 - 64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics

AU - Kobayashi, S.

AU - Amanuma, K.

AU - Mori, H.

AU - Kasai, N.

AU - Maejima, Y.

AU - Seike, A.

AU - Tanabe, N.

AU - Tatsumi, T.

AU - Yamada, J.

AU - Miwa, T.

AU - Koike, H.

AU - Hada, H.

AU - Toyoshima, H.

PY - 2000/12/1

Y1 - 2000/12/1

N2 - Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64Kbit CMVP FeRAM macro is integrated with 0.35μm 3-level metallization CMOS logic devices. The ferroeletric properties of the PZT capacitor formed below 430°C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25°C and 150°C with write/read voltages between 2.7V and 5.5V.

AB - Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64Kbit CMVP FeRAM macro is integrated with 0.35μm 3-level metallization CMOS logic devices. The ferroeletric properties of the PZT capacitor formed below 430°C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25°C and 150°C with write/read voltages between 2.7V and 5.5V.

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JO - Technical Digest - International Electron Devices Meeting

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T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

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