Abstract
Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64Kbit CMVP FeRAM macro is integrated with 0.35μm 3-level metallization CMOS logic devices. The ferroeletric properties of the PZT capacitor formed below 430°C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25°C and 150°C with write/read voltages between 2.7V and 5.5V.
| Original language | English |
|---|---|
| Pages (from-to) | 783-786 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting |
| Publication status | Published - 2000 Dec 1 |
| Externally published | Yes |
| Event | 2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 2000 Dec 10 → 2000 Dec 13 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
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Kobayashi, S., Amanuma, K., Mori, H., Kasai, N., Maejima, Y., Seike, A., Tanabe, N., Tatsumi, T., Yamada, J., Miwa, T., Koike, H., Hada, H., & Toyoshima, H. (2000). 64Kbit CMVP FeRAM macro with reliable retention/imprint characteristics. Technical Digest - International Electron Devices Meeting, 783-786.