63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.

Tohru Nakamura, Kiyoji Ikeda, Kazuo Nakazato, Katsuyoshi Washio, Mitsuo Namba, Tetsuya Hayashida

Research output: Contribution to journalConference article

10 Citations (Scopus)

Abstract

A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.

Original languageEnglish
Pages (from-to)472-475
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
Publication statusPublished - 1986
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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