63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.

Tohru Nakamura; Kiyoji Ikeda; Kazuo Nakazato; Katsuyoshi Washio; Mitsuo Namba; Tetsuya Hayashida

doi:10.1109/iedm.1986.191223

63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.

Tohru Nakamura, Kiyoji Ikeda, Kazuo Nakazato, Katsuyoshi Washio, Mitsuo Namba, Tetsuya Hayashida

Research output: Contribution to journal › Conference article › peer-review

11 Citations (Scopus)

Abstract

A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.

Original language	English
Pages (from-to)	472-475
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/iedm.1986.191223
Publication status	Published - 1986
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/iedm.1986.191223

Cite this

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title = "63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.",

abstract = "A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.",

author = "Tohru Nakamura and Kiyoji Ikeda and Kazuo Nakazato and Katsuyoshi Washio and Mitsuo Namba and Tetsuya Hayashida",

year = "1986",

doi = "10.1109/iedm.1986.191223",

language = "English",

pages = "472--475",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

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T1 - 63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.

AU - Nakamura, Tohru

AU - Ikeda, Kiyoji

AU - Nakazato, Kazuo

AU - Washio, Katsuyoshi

AU - Namba, Mitsuo

AU - Hayashida, Tetsuya

PY - 1986

Y1 - 1986

N2 - A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.

AB - A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.

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U2 - 10.1109/iedm.1986.191223

DO - 10.1109/iedm.1986.191223

M3 - Conference article

AN - SCOPUS:0023014326

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EP - 475

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

ER -

63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.

Abstract

ASJC Scopus subject areas

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