55 ns 16 Mb DRAM

Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; Kuniaka Koyama

55 ns 16 Mb DRAM

Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaka Koyama

Research output: Contribution to journal › Conference article › peer-review

10 Citations (Scopus)

Abstract

The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm² chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 μm MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.

Original language	English
Pages (from-to)	246-247, 353
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	32
Publication status	Published - 1989
Externally published	Yes
Event	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA Duration: 1989 Feb 15 → 1989 Feb 17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

55 ns 16 Mb DRAM. / Takeshima, Toshio; Takada, Masahide; Koike, Hiroki; Watanabe, Hiroshi; Koshimaru, Shigeru; Mitake, Kenjiro; Kikuchi, Wataru; Tanigawa, Takaho; Murotani, Tatsunori; Noda, Kenji; Tasaka, Kazuhiro; Yamanaka, Koji; Koyama, Kuniaka.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 32, 1989, p. 246-247, 353.

Research output: Contribution to journal › Conference article › peer-review

Takeshima, Toshio ; Takada, Masahide ; Koike, Hiroki ; Watanabe, Hiroshi ; Koshimaru, Shigeru ; Mitake, Kenjiro ; Kikuchi, Wataru ; Tanigawa, Takaho ; Murotani, Tatsunori ; Noda, Kenji ; Tasaka, Kazuhiro ; Yamanaka, Koji ; Koyama, Kuniaka. / 55 ns 16 Mb DRAM. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 1989 ; Vol. 32. pp. 246-247, 353.

@article{75a6ff4371c644b0b8a06792be7d82e3,

title = "55 ns 16 Mb DRAM",

abstract = "The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm2 chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 μm MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.",

author = "Toshio Takeshima and Masahide Takada and Hiroki Koike and Hiroshi Watanabe and Shigeru Koshimaru and Kenjiro Mitake and Wataru Kikuchi and Takaho Tanigawa and Tatsunori Murotani and Kenji Noda and Kazuhiro Tasaka and Koji Yamanaka and Kuniaka Koyama",

year = "1989",

language = "English",

volume = "32",

pages = "246--247, 353",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) ; Conference date: 15-02-1989 Through 17-02-1989",

}

TY - JOUR

T1 - 55 ns 16 Mb DRAM

AU - Takeshima, Toshio

AU - Takada, Masahide

AU - Koike, Hiroki

AU - Watanabe, Hiroshi

AU - Koshimaru, Shigeru

AU - Mitake, Kenjiro

AU - Kikuchi, Wataru

AU - Tanigawa, Takaho

AU - Murotani, Tatsunori

AU - Noda, Kenji

AU - Tasaka, Kazuhiro

AU - Yamanaka, Koji

AU - Koyama, Kuniaka

PY - 1989

Y1 - 1989

N2 - The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm2 chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 μm MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.

AB - The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm2 chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 μm MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.

UR - http://www.scopus.com/inward/record.url?scp=0024903014&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024903014&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024903014

VL - 32

SP - 246-247, 353

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

T2 - IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)

Y2 - 15 February 1989 through 17 February 1989

ER -

55 ns 16 Mb DRAM

Abstract

ASJC Scopus subject areas

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