500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach

M. Murugesan; T. Fukushima; Mitsumasa Koyanagi

doi:10.1109/ASMC.2019.8791781

500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach

M. Murugesan, T. Fukushima, Mitsumasa Koyanagi

ENG - Mechanical Systems Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.

Original language	English
Title of host publication	2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538676011
DOIs	https://doi.org/10.1109/ASMC.2019.8791781
Publication status	Published - 2019 May
Event	30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019 - Saratoga Springs, United States Duration: 2019 May 6 → 2019 May 9

Publication series

Name	ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings
Volume	2019-May
ISSN (Print)	1078-8743

Conference

Conference	30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019
Country	United States
City	Saratoga Springs
Period	19/5/6 → 19/5/9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Engineering(all)
Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ASMC.2019.8791781

Fingerprint Dive into the research topics of '500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach'. Together they form a unique fingerprint.

Cite this

Murugesan, M., Fukushima, T., & Koyanagi, M. (2019). 500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach. In 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019 [8791781] (ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASMC.2019.8791781

500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach. / Murugesan, M.; Fukushima, T.; Koyanagi, Mitsumasa.

2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8791781 (ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Murugesan, M, Fukushima, T & Koyanagi, M 2019, 500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach. in 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019., 8791781, ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019, Saratoga Springs, United States, 19/5/6. https://doi.org/10.1109/ASMC.2019.8791781

Murugesan M, Fukushima T, Koyanagi M. 500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach. In 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8791781. (ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings). https://doi.org/10.1109/ASMC.2019.8791781

Murugesan, M. ; Fukushima, T. ; Koyanagi, Mitsumasa. / 500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach. 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings).

@inproceedings{82993c6b5f1040489a74180bb1f2d6a8,

title = "500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach",

abstract = "A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.",

author = "M. Murugesan and T. Fukushima and Mitsumasa Koyanagi",

year = "2019",

month = may,

doi = "10.1109/ASMC.2019.8791781",

language = "English",

series = "ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019",

note = "30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019 ; Conference date: 06-05-2019 Through 09-05-2019",

}

TY - GEN

T1 - 500 nm-sized Ni-TSVwith aspect ratio 20 for future 3D-LSIs-A low-cost electroless-Ni plating approach

AU - Murugesan, M.

AU - Fukushima, T.

AU - Koyanagi, Mitsumasa

PY - 2019/5

Y1 - 2019/5

N2 - A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.

AB - A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.

UR - http://www.scopus.com/inward/record.url?scp=85071025219&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85071025219&partnerID=8YFLogxK

U2 - 10.1109/ASMC.2019.8791781

DO - 10.1109/ASMC.2019.8791781

M3 - Conference contribution

AN - SCOPUS:85071025219

T3 - ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

BT - 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 30th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2019

Y2 - 6 May 2019 through 9 May 2019

ER -