To realize low-power wireless transceivers, it is required to improve the performance of a frequency synthesizer, which is typically used as a frequency multiplier and is composed of a phase-locked loop (PLL). However a general PLL consumes much power and occupies a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), in which spurious signals are suppressed by using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18mm 1P5M CMOS process. The core size was 10.8mm x 10.5mm. The power consumption of the ILO is 9.6mW at 250MHz, and 1.47mW at 4.8GHz. The phase noise is -108dBc/Hz at 1MHz offset. For a ten-times frequency multiplier, output phase noise is 10dB larger than the input phase noise below 10kHz offset, which is the theoretical limit.