43μW 6GHz CMOS divide-by-3 frequency divider based on three-phase harmonic injection locking

Mizuki Motoyoshi, Minoru Fujishima

Research output: Contribution to conferencePaper

27 Citations (Scopus)

Abstract

A harmonic injection-locked divider (HILD) is effective for realizing a low-power phase-locked loop (PLL) circuit because the high-frequency output of a voltage-controlled oscillator (VCO) is down-converted into a low-frequency signal instantaneously. Conventional resonator-based HILDs, however, occupy a large chip area and exhibit a narrow locking range because either an LC or short-stub resonator is required. Ring-oscillator-based HILDs, on the other hand, operate at a relatively low frequency, again with a narrow locking range. In a this study, a new HILD based on three-phase harmonic injection locking is proposed, which realizes a small chip area, a low power consumption, and a wide locking range. As a result of fabrication with 0.18μm CMOS, a divide-by-three HILD is realized with a power consumption of 43μW, a maximum operating frequency of 6GHz, and a locking range of 80% at a supply voltage of 0.7V. The core size is 10.8μm × 10.5μm

Original languageEnglish
Pages183-186
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
Duration: 2006 Nov 132006 Nov 15

Other

Other2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
CountryChina
CityHangzhou
Period06/11/1306/11/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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