40-Gb/s serial-to-parallel and parallel-to-serial conversion with an optically clocked transistor array

Ryohei Urata, Ryo Takahashi, Tetsuya Suemitsu, Hiroyuki Suzuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have fabricated an optically clocked transistor array in a 0.18-μm-gate-length high-electron-mobility-transistor technology for dual serial-to-parallel and parallel-to-serial conversion (time demux/mux) of asynchronous optical packets. An eight channel array demonstrates 40-Gb/s serial-to-parallel and parallel-to-serial conversion.

Original languageEnglish
Title of host publicationProceedings - Thirteenth International Symposium on Temporal Representation and Reasoning, TIME 2006
Publication statusPublished - 2006 Dec 14
Externally publishedYes
Event2006 Optical Fiber Communication Conference, and the 2006 National Fiber Optic Engineers Conference - Anaheim, CA, United States
Duration: 2006 Mar 52006 Mar 10

Publication series

Name2006 Optical Fiber Communication Conference, and the 2006 National Fiber Optic Engineers Conference
Volume2006

Other

Other2006 Optical Fiber Communication Conference, and the 2006 National Fiber Optic Engineers Conference
CountryUnited States
CityAnaheim, CA
Period06/3/506/3/10

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Urata, R., Takahashi, R., Suemitsu, T., & Suzuki, H. (2006). 40-Gb/s serial-to-parallel and parallel-to-serial conversion with an optically clocked transistor array. In Proceedings - Thirteenth International Symposium on Temporal Representation and Reasoning, TIME 2006 [1636966] (2006 Optical Fiber Communication Conference, and the 2006 National Fiber Optic Engineers Conference; Vol. 2006).