4-bit SFQ multiplier based on booth encoder

Ryosuke Nakamoto, Sakae Sakuraba, Takeshi Onomi, Shigeo Sato, Koji Nakajima

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

Original languageEnglish
Article number5680955
Pages (from-to)852-855
Number of pages4
JournalIEEE Transactions on Applied Superconductivity
Volume21
Issue number3 PART 1
DOIs
Publication statusPublished - 2011 Jun 1

Keywords

  • FFT
  • Multiplier
  • SFQ
  • Superconductive circuits

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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