4 40-Gbit/s-class universal logic interfacer IP using GaAs HBT's for heterogeneous logic/device systems in package

Taiichi Otsuji, Seigo Takahashi, Noburo Hamasuna, Toshiaki Takada, Yutaka Matsuoka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 40-Gbit/s-class ECL/SCFL-to-LVCMOS/LVDS universal logic interfacer IP was developed using production-level GaAs HBT's for use in a heterogeneous logic/device system in package (SiP). A unique co-design concept based on the flat and modular IP configurations was introduced to make ease of seamless/universal interconnection with reduced design/test costs. The test chip demonstrated excellent universal level-transform functions with a small power-delay product of less than 2.8 pJ.

Original languageEnglish
Title of host publicationIEEE Compound Semiconductor Integrated Circuit Symposium; 2004 IEEE CSIC Symposium, 26th Anniversary
Subtitle of host publicationCompounding Your Chips in Monterey - Technical Digest 2004
Pages251-254
Number of pages4
DOIs
Publication statusPublished - 2004 Dec 1
Externally publishedYes
EventIEEE Compound Semiconductor Integrated Circuit Symposium; 2004 IEEE CSIC Symposium - Monterey, CA, United States
Duration: 2004 Oct 242004 Oct 27

Publication series

NameTechnical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
ISSN (Print)1550-8781

Other

OtherIEEE Compound Semiconductor Integrated Circuit Symposium; 2004 IEEE CSIC Symposium
CountryUnited States
CityMonterey, CA
Period04/10/2404/10/27

Keywords

  • ECL
  • GaAs HBT
  • LVCMOS
  • LVDS
  • Logic interface
  • SCFL
  • SiP

ASJC Scopus subject areas

  • Engineering(all)

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