3D Super chip technology to achieve low-power and high-performance system-on-a chip

Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A new three-dimensional (3D) integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration has been developed to achieve low-power and high-performance system-on-a chip (SoC). A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

Original languageEnglish
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages61-62
Number of pages2
DOIs
Publication statusPublished - 2011 Sep 19
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: 2011 Aug 12011 Aug 3

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CountryJapan
CityFukuoka
Period11/8/111/8/3

Keywords

  • Three-dimensional (3D) LSI
  • Through-Si via (TSV)
  • microbump
  • self-assembly

ASJC Scopus subject areas

  • Engineering(all)

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