3D memory chip stacking by multi-layer self-assembly technology

Takafumi Fukushima; Jichoru Be; M. Murugesan; H. Y. Son; M. S. Suh; K. Y. Byun; N. S. Kim; Kanuku Ri; Mitsumasa Koyanagi

doi:10.1109/3DIC.2013.6702360

3D memory chip stacking by multi-layer self-assembly technology

Takafumi Fukushima, Jichoru Be, M. Murugesan, H. Y. Son, M. S. Suh, K. Y. Byun, N. S. Kim, Kanuku Ri, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.

Original language	English
Title of host publication	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOIs	https://doi.org/10.1109/3DIC.2013.6702360
Publication status	Published - 2013 Dec 1
Event	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States Duration: 2013 Oct 2 → 2013 Oct 4

Publication series

Name	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Other

Other	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
Country/Territory	United States
City	San Francisco, CA
Period	13/10/2 → 13/10/4

Keywords

3D Chip Stack
Memory
Microbump
Self-Assembly
TSV

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Science Applications

Access to Document

10.1109/3DIC.2013.6702360

Cite this

Fukushima, T., Be, J., Murugesan, M., Son, H. Y., Suh, M. S., Byun, K. Y., Kim, N. S., Ri, K., & Koyanagi, M. (2013). 3D memory chip stacking by multi-layer self-assembly technology. In 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 [6702360] (2013 IEEE International 3D Systems Integration Conference, 3DIC 2013). https://doi.org/10.1109/3DIC.2013.6702360

3D memory chip stacking by multi-layer self-assembly technology. / Fukushima, Takafumi ; Be, Jichoru; Murugesan, M.; Son, H. Y.; Suh, M. S.; Byun, K. Y.; Kim, N. S.; Ri, Kanuku; Koyanagi, Mitsumasa.

2013 IEEE International 3D Systems Integration Conference, 3DIC 2013. 2013. 6702360 (2013 IEEE International 3D Systems Integration Conference, 3DIC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fukushima, T , Be, J, Murugesan, M, Son, HY, Suh, MS, Byun, KY, Kim, NS, Ri, K & Koyanagi, M 2013, 3D memory chip stacking by multi-layer self-assembly technology. in 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013., 6702360, 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, San Francisco, CA, United States, 13/10/2. https://doi.org/10.1109/3DIC.2013.6702360

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abstract = "Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.",

keywords = "3D Chip Stack, Memory, Microbump, Self-Assembly, TSV",

author = "Takafumi Fukushima and Jichoru Be and M. Murugesan and Son, {H. Y.} and Suh, {M. S.} and Byun, {K. Y.} and Kim, {N. S.} and Kanuku Ri and Mitsumasa Koyanagi",

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AU - Suh, M. S.

AU - Byun, K. Y.

AU - Kim, N. S.

AU - Ri, Kanuku

AU - Koyanagi, Mitsumasa

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N2 - Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.

AB - Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.

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KW - Memory

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3D memory chip stacking by multi-layer self-assembly technology

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Keywords

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