3D LSI and reliability

Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Furthermore, design and test methodologies to improve the reliability of 3D LSIs are discussed.

Original languageEnglish
Title of host publication18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2011
DOIs
Publication statusPublished - 2011 Sep 15
Event18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2011 - Incheon, Korea, Republic of
Duration: 2011 Jul 42011 Jul 7

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2011
CountryKorea, Republic of
CityIncheon
Period11/7/411/7/7

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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