3D integration technology and reliability challenges

Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-μm induced the maximum compressive stress of ∼1 GPa at the Si substrate adjacent to them after annealed at 300°C. Mechanical strain/stress and crystal defects were produced in extremely thin wafer of 10μm thickness not only during the thinning but also after the bonding using fine-pitch, high-density metal bump. The influences of Cu contamination from the back surface of the thinned wafer and Cu TSVs on device reliability were evaluated by C-t analysis. The C-t curves of MOS capacitors formed in the thinned wafer without IG layer were seriously degraded after annealed at 200°C. The DP stress-relief EG layer at the backside of the thinned wafer exhibited good Cu retardation performance. The C-t curves of the MOS trench capacitor with 10-nm thick Ta barrier layer in Cu TSV were severely degraded after the initial annealing at 300°C for 5min. The degraded C-t curve indicates that the generation lifetime of minority carrier is significantly reduced by Cu contamination.

Original languageEnglish
Title of host publication2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou, China
Duration: 2011 Dec 122011 Dec 14

Publication series

Name2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Other

Other2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
CountryChina
CityHanzhou
Period11/12/1211/12/14

Keywords

  • 3D-LSI
  • Cu contamination
  • TSV
  • mechanical stress
  • microbump
  • minority carrier lifetime

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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