3D integration technology and reliability

Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20μm induced the maximum compressive stress of ∼1 GPa at the silicon substrate adjacent to them after annealed at 300°C for 30 min. Mechanical strain/stress and crystal defects were produced in extremely thin wafers (thickness ∼10μm) of 3D LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density metal microbumps and curing. The influence of Cu contamination at the back surface of the thinned wafer has been evaluated by C-t analysis. C-t curves measured in MOS capacitors without IG layer and EG layer were seriously degraded after annealing even at 200°C whereas the C-t curves exhibited only a little change even after annealing up to 350 min at 300°C. It was revealed that the generation lifetime of minority carrier is significantly reduced by the Cu contamination.

Original languageEnglish
Title of host publication2011 International Reliability Physics Symposium, IRPS 2011
DOIs
Publication statusPublished - 2011 Jun 23
Event49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States
Duration: 2011 Apr 102011 Apr 14

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other49th International Reliability Physics Symposium, IRPS 2011
CountryUnited States
CityMonterey, CA
Period11/4/1011/4/14

Keywords

  • 3D LSI
  • Cu contamination
  • Mechanical stress
  • Microbump
  • TSV

ASJC Scopus subject areas

  • Engineering(all)

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