3D Integration technologies using self-assembly and electrostatic temporary multichip bonding

T. Fukushima, H. Hashiguchi, J. Bea, M. Murugesan, K. W. Lee, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 μm was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and then formed through-silicon vias (TSVs) for the self-assembled KGDs to fabricate 3D-stacked chips with Cu-TSVs and Cu/SnAg microbumps. By using the new multichip-to-wafer 3D integration process with SAE bonding, we obtained good electrical characteristics from the self-assembled KGDs having Cu-TSVs and Cu/SnAg microbumps.

Original languageEnglish
Title of host publication2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
Pages58-63
Number of pages6
DOIs
Publication statusPublished - 2013
Event2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States
Duration: 2013 May 282013 May 31

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Other

Other2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
CountryUnited States
CityLas Vegas, NV
Period13/5/2813/5/31

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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