3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

Naoya Onizawa, Tomokazu Ikeda, Takahiro Hanyu, Vincent C. Gaudet

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

This paper presents a high-speed low-density parity-check (LDPC) decoder chip using a new decoding algorithm, called a flooding-type update-schedule algorithm. Since node computations are performed using partially updated messages in the proposed algorithm, because of the good similarity among time-consecutive messages, data-transmission bottleneck between nodes for node computation is greatly reduced. Moreover, longer wires between nodes are appropriately divided into several subwires by inserting flip-flops so that system clock frequency for the LDPC decoding scheme can be much increased while maintaining the same BER as a conventional algorithm using fully updated messages. In fact, a throughput of 3.2Gb/s in a 1024-b LDPC decoder chip under 90nm CMOS technology is attained with the sufficient BER.

Original languageEnglish
Title of host publication2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
Pages217-220
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, Canada
Duration: 2007 Aug 52007 Aug 8

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
CountryCanada
CityMontreal, QC
Period07/8/507/8/8

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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