3-D vertical FG NAND flash memory with a novel electrical S/D technique using the extended sidewall control gate

Moon Sik Seo, Sung Kye Park, Tetsuo Endoh

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

We propose a novel 3-D vertical floating-gate (FG) nand Flash memory cell array with a novel electrical source/drain (S/D) technique using extended sidewall control gates (ESCGs). A cylindrical FG structure is implemented to overcome the reliability issues of charge-trap-type cells. A novel electrical S/D layer by the ESCG structure also allows enhancement-mode operation. With this novel structure, we successfully demonstrate normal Flash cell operation with high-speed programming and superior read currents due to both the increase in coupling ratio and the use of low resistive electrical S/D technique by device simulation. Moreover, we found that the 3-D vertical Flash memory cell array with the novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with the conventional 3-D vertical FG nand cell array without an ESCG. Above all, the proposed cell array is one of the candidates for a Terabit 3-D vertical nand Flash cell array with high-speed read/program operation and high reliability.

Original languageEnglish
Article number5962356
Pages (from-to)2966-2973
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume58
Issue number9
DOIs
Publication statusPublished - 2011 Sep

Keywords

  • 3-D vertical stacked cell
  • Extended sidewall control gate (ESCG)
  • floating-gate (FG)-type cell
  • nand Flash memory
  • sidewall control gate (SCG)
  • stacked-surrounding gate transistor (S-SGT)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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