3-D Sidewall Interconnect Formation Climbing over Self-Assembled KGDs for Large-Area Heterogeneous Integration

Takafumi Fukushima, Akihiro Noriki, Jichoel Bea, Mariappan Murugesan, Hisashi Kino, Koji Kiyoyama, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-Area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately 20mu \text{m} ) climbing over 100-\mu \text{m}-Thick self-Assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly 10~\mu \text{m} are successfully formed across polyimide slopes formed on the sidewall of self-Assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-Assembled chips.

Original languageEnglish
Article number7935530
Pages (from-to)2912-2918
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume64
Issue number7
DOIs
Publication statusPublished - 2017 Jul

Keywords

  • Capillary self-Assembly
  • direct bonding
  • heterogeneous integration
  • large-Area chip on substrate
  • sidewall interconnect

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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