TY - JOUR
T1 - 3-D Sidewall Interconnect Formation Climbing over Self-Assembled KGDs for Large-Area Heterogeneous Integration
AU - Fukushima, Takafumi
AU - Noriki, Akihiro
AU - Bea, Jichoel
AU - Murugesan, Mariappan
AU - Kino, Hisashi
AU - Kiyoyama, Koji
AU - Ri, Kanuku
AU - Tanaka, Tetsu
AU - Koyanagi, Mitsumasa
N1 - Funding Information:
Manuscript received March 27, 2017; revised May 12, 2017; accepted May 13, 2017. Date of publication May 30, 2017; date of current version June 19, 2017. This work was supported by the New Energy and Industrial Technology Development Organization through “Highly Integrated, Complex MEMS Production Technology Development Project.” The review of this paper was arranged by Editor M. S. Bakir. (Corresponding author: Takafumi Fukushima.) T. Fukushima is with the Department of Mechanical Systems Engineering, Tohoku University, Sendai 980-8579, Japan (e-mail: fukushima@lbc.mech. tohoku.ac.jp).
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2017/7
Y1 - 2017/7
N2 - Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-Area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately 20mu \text{m} ) climbing over 100-\mu \text{m}-Thick self-Assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly 10~\mu \text{m} are successfully formed across polyimide slopes formed on the sidewall of self-Assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-Assembled chips.
AB - Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-Area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately 20mu \text{m} ) climbing over 100-\mu \text{m}-Thick self-Assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly 10~\mu \text{m} are successfully formed across polyimide slopes formed on the sidewall of self-Assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-Assembled chips.
KW - Capillary self-Assembly
KW - direct bonding
KW - heterogeneous integration
KW - large-Area chip on substrate
KW - sidewall interconnect
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U2 - 10.1109/TED.2017.2705562
DO - 10.1109/TED.2017.2705562
M3 - Article
AN - SCOPUS:85028358102
SN - 0018-9383
VL - 64
SP - 2912
EP - 2918
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 7
M1 - 7935530
ER -