3-D integration technology for realizing super chip

Tetsu Tanaka, Takafumi Fukushima, Mitsumasa Koyanagi

Research output: Contribution to conferencePaper

Abstract

We have described key 3-D integration technologies for realizing the super-chip including through-Si via (TSV) formation, chip self-assembly, and boning. Regarding the TSV formation, we developed the low temperature W CVD process for low resistive interconnections. We also described a novel 3-D integration technology with chip self-assembly. In the super-chip integration technology, a large number of LSI chips can be simultaneously, quickly, and precisely aligned and bonded onto LSI wafers. We successfully fabricated several prototype 3-D LSI chips by using the super-chip integration technology.

Original languageEnglish
Pages197-202
Number of pages6
Publication statusPublished - 2008 Dec 1
Event25th International VLSI Multilevel Interconnection Conference, VMIC 2008 - Fremont, CA, United States
Duration: 2008 Oct 282008 Oct 30

Other

Other25th International VLSI Multilevel Interconnection Conference, VMIC 2008
CountryUnited States
CityFremont, CA
Period08/10/2808/10/30

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Tanaka, T., Fukushima, T., & Koyanagi, M. (2008). 3-D integration technology for realizing super chip. 197-202. Paper presented at 25th International VLSI Multilevel Interconnection Conference, VMIC 2008, Fremont, CA, United States.