2Mb SPRAM design: Bi-directional current write and parallelizing-direction current read schemes based on spin-transfer torque switching

R. Takemura, T. Kawahara, K. Miura, J. Hayakawa, S. Ikeda, Y. M. Lee, R. Sasaki, Y. Goto, K. Ito, T. Meguro, F. Matsukura, H. Takahashi, H. Matsuoka, H. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 1.8V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2-μm logic process with MgO tunneling barrier cell demonstrates the circuit technologies for potential low power non-volatile RAM, or universal memory. This chip features: an array scheme with bit-by-bit bi-directional current write to achieve proper spin-transfer torque writing of 100-ns, and parallelizing- direction current reading with low voltage bit-line that leads to 40-ns access time.

Original languageEnglish
Title of host publicationProceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages238-241
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States
Duration: 2007 May 302007 Jun 1

Publication series

NameProceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
CountryUnited States
CityAustin, TX
Period07/5/3007/6/1

Keywords

  • Low power RAM
  • Nonvolatile RAM
  • Spin-transfer torque
  • TMR
  • Universal RAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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