2Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read

T. Kawahara, R. Takemura, K. Miura, J. Hayakawa, S. Ikeda, Y. Lee, R. Sasaki, Y. Goto, K. Ito, T. Meguro, F. Matsukura, H. Takahashi, H. Matsuoka, H. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

157 Citations (Scopus)

Abstract

A 1.8V 2Mb spin-transfer torque RAM chip using a 0.2μm logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power non-volatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bidirectional current write to achieve proper spin-transfer torque writing in 100ns, and parallelizing-direction current reading with a low-voltage bitline that leads to 40ns access time.

Original languageEnglish
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages480-481+617+471
DOIs
Publication statusPublished - 2007 Sep 27
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 2007 Feb 112007 Feb 15

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/TerritoryUnited States
CitySan Francisco, CA
Period07/2/1107/2/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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