A high-speed 8x8-bit parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's complement multiplication algorithm with carry save adder (CSA) arrays and carry lookahead adders (CLA’s) is employed. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication time is 2.7 ns with a power dissipation of 900 mW.
ASJC Scopus subject areas
- Electrical and Electronic Engineering