2.7-ns 8 x 8-bit Parallel Array Multiplier Using Sidewall Base Contact Structure

Katsuyoshi Washio, Kazuo Nakazato, Tohru Nakamura

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

A high-speed 8x8-bit parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's complement multiplication algorithm with carry save adder (CSA) arrays and carry lookahead adders (CLA’s) is employed. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication time is 2.7 ns with a power dissipation of 900 mW.

Original languageEnglish
Pages (from-to)613-614
Number of pages2
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number4
DOIs
Publication statusPublished - 1987 Aug
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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