2.7-ns 8 x 8-bit Parallel Array Multiplier Using Sidewall Base Contact Structure

Katsuyoshi Washio; Kazuo Nakazato; Tohru Nakamura

doi:10.1109/JSSC.1987.1052779

2.7-ns 8 x 8-bit Parallel Array Multiplier Using Sidewall Base Contact Structure

Katsuyoshi Washio, Kazuo Nakazato, Tohru Nakamura

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

A high-speed 8x8-bit parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's complement multiplication algorithm with carry save adder (CSA) arrays and carry lookahead adders (CLA’s) is employed. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication time is 2.7 ns with a power dissipation of 900 mW.

Original language	English
Pages (from-to)	613-614
Number of pages	2
Journal	IEEE Journal of Solid-State Circuits
Volume	22
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.1987.1052779
Publication status	Published - 1987 Aug
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1987.1052779

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abstract = "A high-speed 8x8-bit parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's complement multiplication algorithm with carry save adder (CSA) arrays and carry lookahead adders (CLA{\textquoteright}s) is employed. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication time is 2.7 ns with a power dissipation of 900 mW.",

author = "Katsuyoshi Washio and Kazuo Nakazato and Tohru Nakamura",

year = "1987",

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AU - Nakazato, Kazuo

AU - Nakamura, Tohru

PY - 1987/8

Y1 - 1987/8

N2 - A high-speed 8x8-bit parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's complement multiplication algorithm with carry save adder (CSA) arrays and carry lookahead adders (CLA’s) is employed. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication time is 2.7 ns with a power dissipation of 900 mW.

AB - A high-speed 8x8-bit parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's complement multiplication algorithm with carry save adder (CSA) arrays and carry lookahead adders (CLA’s) is employed. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication time is 2.7 ns with a power dissipation of 900 mW.

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2.7-ns 8 x 8-bit Parallel Array Multiplier Using Sidewall Base Contact Structure

Abstract

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