2400-MFLOPS reconfigurable parallel VLSI processor for robot control

Yoshichika Fujioka, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The architecture of a floating-point reconfigurable parallel VLSI processor is proposed to reduce the latency for robot control, because the computation is performed in a feedback loop. In each processor element (PE), a switching hardware is used to change the connection between the multipliers and the adders, so that the multiply-adders having desired numbers of multipliers can be reconstructed. Since the data transfer is performed by the direct connection between the multipliers and adders, the overhead for data transfer is reduced. The chip evaluation based on 0.8 μm CMOS design rule shows that the latency for resolved acceleration control (RAC) computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 32 μsec which is about sixty times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Robotics and Automation
PublisherPubl by IEEE
Pages149-154
Number of pages6
ISBN (Print)0818634529
Publication statusPublished - 1993 Jan 1
EventProceedings of the IEEE International Conference on Robotics and Automation - Atlanta, GA, USA
Duration: 1993 May 21993 May 6

Publication series

NameProceedings - IEEE International Conference on Robotics and Automation
Volume3
ISSN (Print)1050-4729

Other

OtherProceedings of the IEEE International Conference on Robotics and Automation
CityAtlanta, GA, USA
Period93/5/293/5/6

ASJC Scopus subject areas

  • Software
  • Control and Systems Engineering
  • Artificial Intelligence
  • Electrical and Electronic Engineering

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